Listar por autor "Liñán Cembrano, Gustavo"
Mostrando ítems 1-20 de 54
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Artículo
A 1000 FPS at 128×128 vision processor with 8-bit digitized I/O
(Institute of Electrical and Electronics Engineers, 2004)This paper presents a mixed-signal programmable chip for high-speed vision applications. It consists of an array of ...
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Ponencia
A 148dB focal-plane tone-mapping QCIF imager
(Institute of Electrical and Electronics Engineers, 2012)This paper presents a QCIF HDR imager where visual information is simultaneously captured and adaptively compressed by an ...
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Artículo
A 151 dB high dynamic range CMOS image sensor chip architecture with tone mapping compression embedded in-pixel
(Institute of Electrical and Electronics Engineers, 2015)This paper presents a high dynamic range CMOS image sensor that implements an in-pixel content-aware adaptive global tone ...
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Ponencia
A 176x144 148dB adaptive tone-mapping imager
(Society of Photo-Optical Instrumentation Engineers, 2012)This paper presents a 176x144 (QCIF) HDR image sensor where visual information is simultaneously captured and adaptively ...
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Artículo
A 3-D Chip Architecture for Optical Sensing and Concurrent Processing
(SPIE, 2010)This paper presents an architecture for the implementation of vision chips in 3-D integration technologies. This ...
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Capítulo de Libro
A focal plane processor for continuous-time 1-D optical correlation applications
(Springer, 2011)This chapter describes a 1-D Focal Plane Processor, which has been designed to run continuous-time optical correlation ...
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Ponencia
A FPP-oriented tone mapping technique for high dynamic range imagers using temporal and final exposure measurements
(Institute of Electrical and Electronics Engineers, 2010)This paper presents a Dynamic Range improvement technique which is specially well-suited to be implemented in Focal Plane ...
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Ponencia
A mismatch-insensitive high-accuracy high-speed continuous-time current comparator in low voltage CMOS
(Institute of Electrical and Electronics Engineers, 1997)This paper presents a CMOS current comparator which employs nonlinear feedback to obtain high-accuracy (down to 1.5 pA) ...
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Ponencia
A mixed-signal early vision chip with embedded image and programming memories and digital I/O
(The International Society for Optical Engineering - SPIE, 2003)From a system level perspective, this paper presents a 128 × 128 flexible and reconfigurable Focal-Plane Analog Programmable ...
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Ponencia
A multimode gray-scale CMOS optical sensor for visual computers
(Institute of Electrical and Electronics Engineers, 2002)This paper presents a new multimode optical sensor architecture for the optical interface of Visual CNN (cellular neural ...
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Ponencia
A processing element architecture for high-density focal plane analog programmable array processors
(Institute of Electrical and Electronics Engineers, 2002)The architecture of the elementary Processing Element - PE- used in a recently designed 128×128 Focal Plane Analog ...
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Ponencia
A QCIF 145dB imager for focal plane processor chips using a tone mapping technique in standard 0.35μm CMOS technology
(2011)This paper presents a QCIF HDR imager where visual information is simultaneously captured and adaptively compressed by ...
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Ponencia
A versatile sensor interface for programmable vision systems-on-chip
(The International Society for Optical Engineering - SPIE, 2003)This paper describes an optical sensor interface designed for a programmable mixed-signal vision chip. This chip has been ...
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Ponencia
ACE 16k based stand-alone system for real-time pre-processing tasks
(The International Society for Optical Engineering - SPIE, 2005)This paper describes the design of a programmable stand-alone system for real time vision pre-processing tasks. The system's ...
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Ponencia
ACE16K: A 128×128 focal plane analog processor with digital I/O
(Institute of Electrical and Electronics Engineers, 2002)This paper presents a new generation 128×128 focal-plane analog programmable array processor (FPAPAP), from a system level ...
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Ponencia
ACE16k: A programmable focal plane vision processor with 128 x 128 resolution
(European Conference on Circuit Theory and Design, 2001)This paper presents a new generation 128x128 Focal Plane Analog Programmable Array Processor (FPAPAP), from a system ...
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Artículo
ACE16K: The Third Generation of Mixed-Signal SIMD-CNN ACE Chips Toward VSoCs
(Institute of Electrical and Electronics Engineers, 2004)Today, with 0.18-μm technologies mature and stable enough for mixed-signal design with a large variety of CMOS compatible ...
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Ponencia
Analog weight buffering strategy for CNN chips
(Institute of Electrical and Electronics Engineers, 2003)Large, gray-scale CNN chips employ analog signals to achieve high-density in the internal distribution of the template ...
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Artículo
Bifurcations and synchronization using an integrated programmable chaotic circuit
(World Scientific Publishing, 1997)This paper presents a CMOS chip which can act as an autonomous stand-alone unit to generate different real-time chaotic ...
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Artículo
CMOS 2.4μm chaotic oscillator: Experimental verification of chaotic encryption of audio
(Institution of Engineering and Technology, 1996)The Letter reports the first experimental verification of chaotic encryption of audio using custom monolithic chaotic ...